In this course, you will learn to understand, design, test, and implement complex digital hardware.
You will learn to use Verilog, one of the two modern, industry-standard hardware description
languages to develop digital hardware at a much higher level of abstraction than is possible with
schematic-based design methods. Furthermore, you will use industry-standard development hardware in the
form of an Field-Programmable Gate Array (FPGA) based development board. Finally, you will use these
skills to implement a MIPS processor in Verilog.
The textbook for this course is
Digital Design and Computer Architecture, by Daved Money Harris and Sarah L. Harris.
The hardware for this course will be the
Digilent Spartan 3E Starter Board, which uses a
Xilinx Spartan 3E FPGA. This will allow
There are a number of exercises associated with each week of the course. These are designed to help you
learn the material for the week, but they will not be handed in. Depending on which Computer Sciences
courses you have taken, some of the material may be review for you; do the exercises you need to do to learn
the material.
Solutions for all the exercises are availible here.
There are five labs associated with the first seven weeks of the course, and an additional three labs that
comprise the final project. These labs were developed by the textbook authors, and will give you the
opportunity to put your textbook learning into practice, learn how to use the Xilinx ISE design software and
the ModelSim simulation software, and implement your digital circuits in programmable hardware.
Each of the labs has a section entitled "What to Turn In". You can ignore these sections for the first
five labs, as only the final three labs must be handed in. (Exception: the 32-bit ALU will be reused in
the final project.) However, it is strongly recommended you complete all the labs, as skipping the earlier
labs will make it very difficult to develop the skills required to complete the final three.
Please refer to the "What to Turn In" sections of the three labs that comprise the
Final Project.
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