Readings:

• Chapter 4

Key Concepts:

• Behavioral Modeling
• Structural Modeling
• Simulation
• Synthesis
• Combinational Logic in Verilog
• Sequential Logic in Verilog
• Blocking and Nonblocking Assignments
• Finite State Machines in Verilog
• Parameterized Modules
• Testbenches

Exercises:

• Ignore the VHDL part of all of these problems.
• 4.1 - 4.10

Lab: Thunderbird Turn Signal

This will be the first lab to use the Spartan 3E development board.

We will be using the XST synthesis tool instead of the Synplify Pro synthesizer. Thus, where the lab refers to Synplify Pro, use XST instead. To synthesize, make sure your Verilog module is selected in the "Sources" pane, then click "Synthesize - XST" in the "Processes for:" pane. Reading through the Synthesis report should reveal details about how the synthesizer implemented your FSM.

XST will not create a state transition diagram for you. However, if you right select "View RTL Schematic" and then double-click on the FSM block diagram, you can examine the output logic.

As usual, you will not be handing anything in for this assignment, so there is no need to print anything or create a writeup.

For instructions on uploading to the development board, see Lab 2.

Also, be aware that the mechanical switches on the development board may be subject to contact bounce, which may give multiple positive edges when the switch is switched.