Readings:

• 3.5 - 3.7
• 4.1 (p. 171 is key)

Key Concepts:

• Timing Sequential Logic
• The Dynamic Discipline
• Synchronizers
• Latency
• Throughput
• Begin Verilog

Exercises:

• 3.30 - 3.35 (3.32 involves the FPGA we'll actually be using)
• Try 4.1 (ignoring the VHDL) using HDL Example 4.1 on page 168