CS 207
Midterm 2
Ondich
Due 8:30 AM Wednesday, November 12, 2003

For this exam, you may use your textbook, your notes and assignments, your brain, the Math/CS computers, and any psychic powers you may possess. If you get stuck, talk to Jeff Ondich. Do not talk to anyone else about the exam.

Explain and justify your answers. Submit your answers on paper.

  1. (10 points) The following questions concern IEEE 754 32-bit floating point numbers. When I refer to a "representable number," I mean a number whose exact value is one of the values that has a 32-bit IEEE 754 representation.

  2. (3 points) Using the Internet, the library, or your friendly neighborhood RadioShack salesperson, answer the question that has been plaguing us: how much slower than a two-input AND gate is a 3- or 4- or 8-input AND gate. (It will probably be easiest to find data on the 2-input and 4-input gates, and that information will be plenty for full credit. If you find more information, of course, I'd be happy to see it.)

  3. (7 points) Consider the final version of the multiplication hardware discussed in section 4.6 of your textbook, and shown in Figure 4.31 on page 257. Though this multiplier saves a lot of gates over the multiplier in Figure 4.25, it has a problem. The algorithm for Figure 4.25 can terminate when the multiplier is 0, but the algorithm for Figure 4.31 has to iterate 32 times. Show how to enhance Figure 4.31 to allow an early termination of the computation without completely giving away the space savings we got from combining the product with the multiplier. How many extra bits (or how many extra gates, as you wish) do your enhancements add to 4.31?

  4. (10 points) Consider the multi-cycle datapath shown in Figure 5.33 in Patterson and Hennessy. Suppose the PC starts with the value 16000, the instruction at location 16000 of memory is "lw $4, -12($5)", and the contents of registers $4 and $5 are 104 and 8000, respectively. Suppose further that we have executed this instruction up through the very end of its third clock cycle, but that the clock has not yet fallen to end the third cycle and begin the fourth. Print Figure 5.33 and show the values of as many lines on the datapath as possible. This includes control lines, lines whose values are used during this cycle, lines whose values are not used during this cycle, lines whose values are left over from old cycles, etc.

  5. (8 points) Still using Figure 5.33, suppose the propagation delays of the various elements are: 10 ns for memory and the ALU, 4ns for the registers, the Control, and the ALU Control, 2ns for each of the multiplexors, and 1 ns for the shift left, the sign extend, and the individual gates. Also, assume that the memory elements IR, PC, A, B, Memory data register, and ALUOut show the proper output 1ns after the trailing clock edge (assuming the appropriate write-enable lines are set).

    Consider the lw instruction of the previous problem. For each of the five clock cycles it takes to complete this instruction, what amount of time is required to complete that cycle's work? Based only on lw, then, what is the fastest allowable clock rate?

  6. (2 points) Okay, I got your book recommendations. Now, let's hear your favorite movie(s).

  7. (8 points) This problem concerns "byte order" and the related terms "big-endian" and "little-endian," topics that are covered only very briefly by your textbook (on pages A47-48). Therefore, you should look for a better explanation of the subject before answering the following questions. I have placed a copy of "Structured Computer Organization, 4e," by Andrew Tanenbaum, on the bottom shelf of the bookcase in the Math Skills Center--see pages 58-61. There are also many discussions of the topic on the web, including a famous article called "On Holy Wars and a Plea for Peace," by Danny Cohen.